The present invention relates to the field of semiconductor devices. More particularly, the present invention is related to a device and method for forming an extension in a FinFET device.
FinFET (Fin field-effect transistor) is a technology that allows for higher performance in smaller devices. A bulk FinFET structure includes a fin, a gate, and a source drain region. The structure has narrow bars of SiGe (silicon-germanium) fins with a gate or gates on either side of the fins. The gates can also be located on top of the fins. SiGe FinFET devices are designed to help reduce the threshold voltage and improve device performance. The source/drain region of the MOSFET (metal oxide semiconductor field-effect transistor) is doped by adding trace impurity elements into the substrate which allows the electrical properties to be altered. The source/drain region can be doped by either ion implantation or by merging the source/drain regions with an epitaxy layer and doping this epitaxy layer in-situ. After doping is complete, the bulk wafer is annealed for diffusion and activation of the dopant to form the source/drain and extension junctions. Doping with ion implantation causes fin damage and incomplete or no recrystallization upon annealing. This leads to defects and incomplete activation of the dopant, which in turn leads to higher leakage and higher access resistance, respectively. Boron is the common dopant for positive channel field effect transistor (pFET) devices. Diffusion of boron from merged epitaxy layer into the SiGe fins is extremely slow and can leave a significant portion of the SiGe fin undoped, thus leading to underlapped devices with very high access resistance. SiGe FinFET devices with overlapped junction and lower access resistance are a challenge as boron diffusion in SiGe is negligible.